The present invention relates in general to a semiconductor memory device in which an electrically reloadable nonvolatile semiconductor memory is used as a storage medium, and more particularly to a semiconductor memory device employing a semiconductor memory which includes partially faulty cells and which becomes faulty if the reloadable operation is carried out at frequent intervals.
An electrically reloadable nonvolatile memory has more advantageous features as a memory device of an information apparatus in terms of the low power consumption, the resistance against the vibrational shock, the high speed operation and the like as compared with other devices such as a magnetic memory device and an optical disc device. On the other hand, however, since the manufacturing process thereof is complicated and in addition thereto, the operations which are in principle irreversible against semiconductor are repeatedly carried out, there arises a problem that occurrence of faulty portions and degradation in use thereof are remarkable. As a result, the manufacturing yield thereof is poor, the cost required therefor is expensive and reliability in operation thereof becomes a problem.
In order to solve the above-mentioned problems, the technique has been developed such that the faulty portions of the memory are previously registrated so as not to be used, and the number of times of use of the data blocks is recorded and then if this number of times is increased, then the region of interest is replaced with another region to suppress the increase in the number of times of use thereof, thereby increasing the life of the semiconductor memory device. This technique is disclosed in JP-A-6-124596 for example.
According to this disclosed technique, there is provided a memory for storing therein an address conversion table showing the comparison between the logical addresses and the physical addresses, i.e., the correspondence between the logical address specified by a host and the corresponding physical address on the memory. As a result, the physical address of the faulty region is registered in the address conversion table so as to show that it is faulty so that the logical address specified by the host is not assigned thereto, thereby preventing the faulty portion from being used.
In addition, the number of times of erasing is administrated. That is, if the number of times of erasing has reached a fixed value, then the data of the region of interest is replaced with the data of another region and at the same time, the address values on the address conversion table are reloaded to register again the data relating to the correspondence between the logical addresses and the physical addresses so that the proper correspondence therebetween can be obtained. All of the logical address values in use are registered in the above-mentioned address conversion table. Then, the high speed volatile memory such as a DRAM or an SRAM is used as the storage medium for the address conversion table.
The reason of employing the high speed volatile memory is that the address conversion can be carried out at a high speed; when the replacement of the address of interest with another address occurs, the registration can be partially reloaded at a high speed; the mass storage of the data can be realized by utilizing the relatively inexpensive memory; and so forth.
In the above-mentioned prior art, since the registration of the address conversion is carried out with respect to all of the logical addresses, when the memory device becomes of mass storage, the scale of the address conversion table becomes large and hence the mass storage memory for registration is required. In addition, since the memory device is of a volatile type, if the power source is disconnected, then all of the data stored therein will be erased. As a result, when turning on the power source again, all of the registered values need to be written thereto from another nonvolatile memory and hence the time period required for the activation of the memory device is increased. This is a problem.
In addition, since the external memory for registration becomes of mass storage, there arises a problem that the number of components is increased, which disturbs the miniaturization and the promotion of lowering the cost of the memory device.
In addition, if the nonvolatile memory is employed as the above-mentioned memory for registration, then there arises a problem that since the access time of the nonvolatile memory is generally long, the access time of the memory device itself becomes necessarily long.
In addition, if the back-up power source is provided for the volatile memory for registration, then the number of components is further increased, which disturbs the miniaturization and the promotion of lowering the cost of the memory device. This is a problem.
In the light of the foregoing, it is therefore an object of the present invention to provide a mass storage semiconductor memory device, in which the miniaturization thereof and the promotion of lowering the cost thereof can be made, and also the activation time and the access time are reduced, by solving the above-mentioned problems associated with the prior art.
It is a concrete object of the present invention to provide, by either reducing the capacity of the external memory for registration or removing the external memory for registration, a mass storage semiconductor memory device in which the activation time and the access time are both short.
It is a concrete object of the present invention to provide, for use in a mass storage semiconductor memory device in which either the capacity of the external memory for registration is reduced or the external memory for registration is removed, an access method by which both of the activation time and the access time can be made short.
It is another object of the present invention to provide, for use in a mass storage semiconductor memory device in which either the capacity of the external memory for registration is reduced or the external memory for registration is removed, a controller which is capable of realizing the short activation time and access time.
According to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty memory cells each of which is defective in the function for storing data is used as a storage medium, and the holding of the data or the reading of the data thus held is carried out in blocks containing a plurality of data, the semiconductor memory device including: faulty location registering means for registering address values of faulty regions containing therein the memory cells each of which is defective in the storage function in either ascending order or descending order depending on the magnitudes of the address values in blocks; alternative storage regions as storage regions with the address values of which the address values of the faulty regions are replaced in blocks; alternative location registering means for registering the replaced address values which are obtained by replacing the address values of the faulty regions stored in the faulty location registering means with the address values of the alternative regions; fault registration retrieval means for retrieving the faulty location registering means in order to judge whether or not the address value in the region in or from which the data is held or read out corresponds to the address value on the faulty region; access control means for carrying out the control so as, when the address value in the region in or from which the data is held or read out is registered in the faulty location registering means, to access the alternative region by referring to the alternative location registering means; and registration update means for carrying out, when a fault newly occurs, the reloading in accordance with the rule of either the ascending order or descending order in the faulty location registering means, the decision of the alternative location therefor and the update of the alternative location registering means.
In addition, the fault registration retrieval means of the faulty location registering means of the semiconductor device firstly devices the regions of the faulty location registering means into halves to estimate in which side the faulty location is present, and then divides the side of the halves in which the faulty location is estimated to be present into halves to estimate in which side the faulty location is present. By continuing this process, it is finally judged by the fault registration retrieval means whether or not the data relating to the faulty location is registered in the faulty location registering means to carry out the retrieval thereof, thereby realizing the high speed retrieval.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty memory cells each of which is defective in the function of storing data is used as a storage medium, and when holding the data or reading out the data thus held, a fixed amount of data which is continuously transferred is administrated as the data administrative unit, and administrative information storage regions in which administrative information is stored every data administrative unit are provided in the inside of the semiconductor memory, and which includes use frequency administrating means for monitoring the use frequency of the data administrative unit, the semiconductor memory device including administrative information storage regions used to administrate a plurality of memory cells as an administrative storage unit and use frequency administrating means for monitoring the use frequency of blocks, wherein administrative addresses as the logical addresses which are determined for the sake of convenience for administration are registered in the administrative information storage regions of all of the blocks, and the administrative address of interest is made an address matching the physical address which is basically the physical address value of the semiconductor memory so that in the access to the data which is stored in the block specified by the administrative address of interest, the physical address equal to the administrative address of interest is accessed to carry out the desired access, while when it is judged by the use frequency administrating means that the data stored in the block should be exchanged for the data stored in another block which is different in the use frequency therefrom, the data stored in the block of interest is exchanged for the data stored in another block, and during this exchange, the administrative address of the stored data is registered in the administrative information storage region, and in the access to the data stored in subsequent block specified by the administrative address of interest, by referring to the administrative address which is registered in the administrative information storage region of the physical address equal to the administrative address of interest, the physical address equal to the administrative address value thus registered is accessed to obtain the desired data stored in the associated block.
Then, when it is judged by the use frequency administrating means that the data of the block in which the above-mentioned administrative address does not match the above-mentioned physical address due to the fact that the replacement of the data is already carried out needs to be further replaced with the data of another block, after the compatibility of the stored data with the administrative storage unit which became an object when the replacement was carried out at the last time has been released by carrying out the replacement again, the data stored in the region of interest is replaced with the data stored in another region.
In addition, as another means, alternative address registration regions for the overall storage regions of the data, and alternation regions are provided in the inside of the semiconductor memory. The alternative address registration regions are arranged in the registration order in accordance with the physical order for the storage of the data on the memory so that in the retrieval of the alternative addresses, the registered location becomes uniquely clear on the basis of the physical position of the region to which the alternative was made.
Then, an administrative information region is provided every data administrative unit. At least the address information of the stored data, the specific code exhibiting that the region of interest is not faulty, and the error correction code for such administrative information are stored in the administrative information region. When the access request is issued from the outside, the error detection and correction of the corresponding region based on the error correction code, and the comparison with respect to the specific code exhibiting that the region of interest is not faulty are carried out. Then, when both are normal, the region of interest is judged to be the usable region to execute the access processing, while when one of them is not normal, the region of interest is processed as the disusable region.
In addition, the storage regions in which the data of the data administrative units is temporarily stored are provided for two units. Then, the transfer of the data to/from the outside and the transfer of the data to/from the above-mentioned semiconductor memory are carried out alternately, thereby making both the transfer possible at the same time. In addition thereto, the control for carrying out the access with the faulty memory cell avoided is processed in parallel to the transfer of the data to/from the outside.
Since any of the address values of the regions which are not faulty is not registered and only the address value of the region which is faulty is registered, the amount of registered data can be reduced and hence the capacity of the memory for registration can be reduced. In addition, since the faulty addresses are registered in either ascending order or descending order, when retrieving a certain address value, if an arbitrary location within the registration memory is referred, it can be decided rashly whether the certain address value is registered on the side of the address values each smaller than the referred address value or on the side of the address values each larger than the referred address value. From a large amount of registered values as well, it can be judged at a relatively high speed whether or not the certain address value is registered or in which location the certain address value is registered.
In addition, in the case where the region in which the administrative information is stored is provided in each of the blocks of the memory of the storage medium, the logical address value can be registered in that region, and also when the physical location of interest needs to be replaced with another physical location due to the frequent reloading and the like thereof, the logical address value within the administrative information is replaced, thereby being able to cope simply with such a situation. In addition thereto, since those logical address values do not need to be registered in the form of a table in the external memory, there is no need of providing any other volatile memory, and also there is no need of reconstructing the table when turning on the power source.
Then, when in the registration of those logical address values, for the block for which the replacement was carried out one time, the additional replacement is required, the last replacement is returned to the original state and then the required replacement is carried out, whereby the number of times of reference, to the administrative information region, for grasping the logical address values has only to be one at the most and hence the situation in which the reference is forced to be made rotationally can be avoided.
In addition, according to the measure that if the fault registration region for all of the addresses is provided as another means, even if the access should be made to the faulty location, since from that physical location, the location where the alternative address is registered can be uniquely determined, it is possible to shorten greatly the retrieval time. In addition, since the judgement for the fault is carried out on the basis of the two codes, i.e., the error correction code and the specific code exhibiting the region which is not faulty, it is possible to reduce remarkably the probability that the judgement with respect to the fault/nonfault is made by mistake.
In addition, the storage regions in which the transfer data is temporarily stored are provided for two units, and in this connection, one is used in the transfer of the data to/from the outside, while the other is used in the transfer of the data to/from the memory, and those transfers are switched alternately over to each other, which results in both of the transfers being able to be carried out at the same time. In addition thereto, in the case where the speed of the transfer of the data to/from the memory is higher than the speed of the transfer of the data to/from the outside, since the overhead time required for the judgement whether or not the accessed region is faulty and the retrieval of the alternative address can lapse in the background of the transfer of the data to/from the outside, the apparent transfer performance can be improved.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, and when writing, holding or reading out the data to, in or from the storage medium, a fixed amount of data is treated as a data administrative unit, the semiconductor memory including, in the inside thereof, storage regions in which the data of the data administrative unit is stored, alternative regions of the storage regions and address registration regions of the alternative regions, wherein address values showing the respective alternative regions are stored in addresses, within the regions in which the alternative addresses are registered, in accordance with the address values in the storage regions.
In addition, the present invention may provide the semiconductor memory device wherein the storage regions include administrative information, respectively, and store therein, as the administration information, fault judgement information based on which it is judged whether or not each of the storage regions is faulty, and when the access request is made to the storage region of interest, it is judged whether or not the storage region of interest thus accessed thereto is the usable region using the fault judgement information of the storage region of interest, and if it is judged that the storage region of interest is the usable region, then the access processing is executed, while if it is judged that the storage region of interest is not the usable region, then the alternative address registration region is accessed to obtain the desired address, and then the alternative region is accessed.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, and when writing, holding or reading out the data to, in or from the storage medium, a fixed amount of data is treated as a data administrative unit, the semiconductor memory including, in the inside thereof, storage regions in which the data of the data administrative unit is stored, alternative regions of the storage regions and address registration regions of the alternative regions, wherein the storage regions include administrative information, respectively, and store therein, as the administrative information, fault judgement information consisting of correction information based on which the detection and correction of an error of the data stored in the storage regions are carried out and detection information based on which it is detected whether or not each of the storage regions is faulty, and when the access request is made to the storage region of interest, it is judged using the fault judgement information corresponding to the storage region of interest whether or not the storage region of interest thus accessed thereto is the usable region, and if it is judged that the storage region of interest is the usable region, then the access processing is executed.
In addition, the present invention may provide the semiconductor memory device wherein the data which is different from the alternative address value is registered in the registration location of the region which is not faulty in the alternative address registration regions, so that it can be judged whether or not the faulty region is registered.
In addition, the present invention may provide that with respect to the different data, the bits thereof are either all 1s or all 0s.
In addition, the present invention may provide the semiconductor memory device wherein when the access request is made to the storage region of interest, the detection and correction of an error are carried out using the correction information, and when the discorrectable error is detected, the storage region of interest is judged to be the disusable region, while there is no error or when the correctable error is corrected, it is detected using the detection information whether or not the region of interest is faulty, and if it is judged that the region of interest is not faulty, then the region of interest is judged to be the usable region to execute the access processing, while if it is judged that the region of interest is faulty, then the region of interest is processed as the disusable region.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, and when writing, holding or reading out the data to, in or from the storage medium, a fixed amount of data is treated as a data administrative unit, the semiconductor memory device including means for producing and adding fault judgement information based on which for the transfer data resulting from the request of storing data, it is judged whether or not a storage region in which the transfer data has been stored becomes faulty after completion of the storage, wherein when issuing the request of reading out the data thus stored, the fault judgement processing is executed using the fault judgement information, and the storage region which has been judged to be faulty is treated as the faulty region, and also the data which is stored in the faulty region is transferred to the alternative region after having been corrected.
In addition, the present invention may provide that the storage regions in which the stored data of the data administrative unit is temporarily stored are provided for two units and outside the storage medium, and the access processing using the fault judgement information is executed in parallel with the transfer of the data to/from the outside.
In addition, according to the present invention, there is provided a method of accessing to a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, wherein the storage region which is provided in the inside of the semiconductor memory and in which the data is stored is accessed to judge whether or not it is faulty, and if it is judged that the storage region of interest is not faulty, then this access is continued, while if it is judged that the storage region of interest is faulty, then an address registration region of an alternative region is accessed to obtain the address of the alternative region, and the alternative region is accessed on the basis of the address thus obtained.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, the semiconductor memory device including, in the inside thereof, storage regions in which the data of the data administrative unit is stored, alternative regions of the storage regions, and address registration regions of the alternative regions, wherein when accessing to the data stored in the semiconductor memory, a time period required for accessing to the semiconductor memory in the case where the alternative region is not yet substituted for the data storage region is shorter than a time period required for accessing to the semiconductor memory in the case where the alternative region is already substituted for the data storage region.
In addition, according to the present invention, there is provided a semiconductor memory device in which a semiconductor memory having partially faulty cells is used for a part of or all of a storage medium, the semiconductor memory device including, in the inside thereof, storage regions in which the data of the data administrative unit is stored, alternative regions of the storage regions, and address registration regions of the alternative regions, wherein when accessing to the data stored in the semiconductor memory, the number of times of access to the semiconductor memory in the case where the alternative region is not yet substituted for the data storage region is smaller than the number of times of access to the semiconductor memory in the case where the alternative region is already substituted for the data storage region.
In addition, according to the present invention, there is provided a semiconductor memory controller for controlling writing and reading of data to and from a semiconductor memory storage medium having partially faulty cells and including storage regions in which the data of data administrative unit is registered, alternative regions of the storage regions, and address registration regions of the alternative regions, wherein when there is issued a request of accessing to the storage region of interest, using fault judgement information of the storage region of interest exhibiting whether or not the data stored in the storage region of interest is faulty, it is judged whether or not the storage region of interest is a usable region, and if it is judged that the storage region of interest is a usable region, then the access processing is executed.
In addition, the present invention may provide that when there is issued the request of accessing to the storage region of interest, using correction information of the storage region of interest for the data stored in the storage region of interest, the error detection and correction are carried out, and when the discorrectable error has been detected, the storage region of interest is judged to be the disusable region, while when no error has been detected or when the correctable error has been corrected, using detection information of the storage region of interest based on which it is detected whether or not the storage region of interest is faulty, it is detected whether or not the storage region of interest is faulty, and if it is judged that the storage region of interest is not faulty, then the storage region of interest is judged to be the usable region to execute the access processing, while if it is judged that the storage region of interest is faulty, then the storage region of interest is processed as the disusable region.